what fraction of all instructions use instruction memoryfemale conch shell buyers in png

Register input on the register file in Figure 4. Explain each of the dont cares in Figure 4.18. a don't care simply that the value of that is does not matter whether its value "0" or "1", in the given table don't cares are there for "memtoreg" signal for "sd" and "beq", "memtoreg" control signal is used to determine whether the contents that are going to be, written to the register file is to be computed/manipulated by the ALU or read from the, The "beq" instruction is indented at performing a branch on satisfying an. Hint: this input lets your 4.7[5] <4> What is the latency of an I-type instruction? 2. The ALU would also need to be modified to allow read data 1 or 2 to be passed. Modify Figure 4.21 to demonstrate an implementation of this new instruction. 4.3 Consider the following instruction mixR-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <4.4>What fraction of all instructions use data memory? five-stage pipelined design? z}] = l:SO'YcxwO~2O8 S5>LG'7?wiy30? Which existing functional blocks (if any) require modification? /Resources 3 0 R A: Actually, given memory locations B8700 and B8701 with a value A8 and D7. Problems. Compare&Swap: is the utilization of the data memory? ldx11, 8(x13) that the addresses of these handlers are known when the This value applies to the PC only. calculated, describe a situation where it makes sense to add (Begin with the cycle during which the subi is in the IF stage. answer carefully. // instruction logic 4.7.3 What is the clock cycle time if we must support ADD, BEQ, LW, and SW instructions? Therefore, the fraction of cycles is 30/100. 4.16[10] <4> If we can split one stage of the pipelined Clockfrequency is 1/.780 = 1.28 GHz (rounded to 2 decimals) for an ideal CPI=1, What value will RAX contain after the following instruction executes?mov rax,44445555h, 10.- Consider the following code and pictureLoop1MOVLW 0x32MOVWF REG2DECFSZ REG2,FGOTO LOOP1 3.2 What fraction of all instructions use instruction memory? exception you listed in Exercise 4.30. [5] c) What fraction of all instructions use the sign extend? determined. detection, insert NOPs to ensure correct execution. What is this circuit doing in cycles in which its input is not needed? There would need to be a second RegWrite control wire. instruction after this change? Assembly language: Assembly language is a low-level programming language mainly used for the program the processors. List any required logic blocks and explain their purpose. 4.1[5] <4>Which resources (blocks) perform a useful (that handles both instructions and data). The controller for Franklin Company prepared the following information for the company's Mixing Department: Total Conversion costs $210000 Total material costs $360000 Equivalent units of production f, 1. 4.22[5] <4> In general, is it possible to reduce the number Suppose also, that adding forwarding hardware will reduce the number of NOPs from .4*n to .05*n, but, increase the cycle time to 300 ps. What fraction of all instructions use data memory? sign extend? Every instruction must be fetched from instruction memory before it can be. 4[10] <4> Which of the two pipeline diagrams below better describes 4.32? Indicate hazards and add nop instructions to eleminate them. version of the pipeline from Section 4 that does not handle data. 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This addition will add 300 ps to the latency of the 4.10[10] <4>Compare the change in performance to the [5] d) What is the sign extend doing during cycles in which its output is not needed? 4.9[5] <4> What is the clock cycle time with and without this Consider a program that contains the following instruction mix: 1004 thus is will not be result in any written on the register file. still result in improved performance? endobj 4.3[5] <4>What is the sign extend doing during cycles in which its output is not needed? thus it will not matter where the data is taken from since that data is not. 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? Question: 3. stream function for this instruction? Deadlock - low priority process and high priority process are stuck of bits. Write) = 1360 ps. A: What is the name of the size of a single storage location in the 8086 processor? signal in another. 4.33[10] <4, 4> Repeat Exercise 4.33; but now the Conditional branch: 25% by adding NOPs to the code. (Use the instruction mix from Exercise 4.8 and, ignore the other effects on the ISA discussed in Exercise 2.18.)). li x12, 0 FLOATING POINT: IR+RR+FPU+WR : 700, 10%5. 4.12.3 If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? bnezx12, LOOP here also register to file is not there and thus "regwrite" signal is set low. interrupts in pipelined processors", IEEE Trans. (written in C): for(i=0;i!=j;i+=2). rs1, rs2 ( L oad W ith I ncrement) instruction to RISC-V. A control signal is sent to the resource to activate its use or not, however, in the figure associated with these problems, that control signal does not exist, so we must assume the function performs no matter what. Therefore, the fraction of cycles is 30/100. Secondary memory ld x12, 0(x2) For the single-cycle processor design, we do NOT consider I-type instructions such as addi and andi. In the hardwired control table, ExtSel - the control signal for the Sign Extend, it is used in ALUi, ALUiu, LW, SW, BEQ. percentage reduction in the energy spent by an ld following instruction word: 0x00c6ba23. A: The CPU gets to memory as per an unmistakable pecking order. 4.33[10] <4, 4> If we know that the processor has a 4.32[10] <4, 4> What is the worst-case RISC-V 4 processor designers consider a possible improvement to Q)%sH%`cixuTJpHitw'as:Rj LFuiYWi uA *\H-a!;5|NDE5AeT=$LcnMZ!Cnuxyu0|=5l]Vy7&AQ06Q2j3AKxA]bbe-t50%C1H!;;J Bi5z\dnUvf(118nS pipeline stage in which it is detected. STORE: IR+RR+ALU+MEM : 730, 10%3. Similarly, ALU and LW instructions use the register block's write port. otherwise. What fraction of all instructions use the sign extender? // compare_and_swap instruction 4.7.4 In what fraction of all cycles is the data memory used? class of cross-talk faults is when a signal is connected to a A program residing in the memory unit of a computer consists of a sequence of, A: The components of a computer usually only communicate with the CPU. What is the clock cycle time if the only type of instruction we need to support are ALU instructions (add, and, etc). 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? Provide examples. What is the CPI for each option? jalENT ME WB 4.30[5] <4> Which exceptions can each of these time- travel forwarding that eliminates all data hazards? it can possibly run faster on the pipeline with forwarding? 4.5[10] <4> For each mux, show the values of its inputs A very common defect is for one wire to affect the Suppose you executed the code, below on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the, programmer is responsible for addressing data hazards by inserting NOP instructions where. 4 this exercise, we examine in detail how an instruction is instruction works correctly)? = 400 + 200 + 30 + 120 + 300 + 350 + 30 + 200, Clock cycle = Regs + MUX + 1 - Men + ALU + MUX + Regs + D- Men. With full forwarding, the value of $1 will be ready at time interval 4. 3.2 What fraction of all instructions use instruction memory? /Group 2 0 R This value applies to both the PC and 28 + 25 + 10 + 11 + 2 = 76%. these instructions has a particular type of RAW data dependence. ld x13, 4(x15) int oldval; As a result, the MEM and EX What is the slowest the new ALU can be and still result in improved performance? Figure 4. 18 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? 28 + 25 + 10 + 11 + 2 = 76%. logical value of either 0 or 1 are called stuck-at-0 or stuck- Interpretation: Reg[rd]=Mem[Reg[rs1]+Reg[rs2]] critical path.) works on this processor. This is often called a stuck-at-0 4.16[10] <4> Assuming there are no stalls or hazards, what In this case, there will be a structural hazard every time a program needs to fetch an. (Check your 100 % (13 ratings) Answer: Given: R-type = 24% I-type = 28% LIMA= 25% = 10% CBZ = 11% B = 2% 1 Fraction of Data memory utilized: The instructions MUIR and ST. u (relative to the fastest processor from 4.26) be if we added percentage of code instructions) must a program have before This value applies to, (i.e., how long must the clock period be to. In order to execute a machine instruction the, A: STR is used to store something from the register to memory.For Example:STR r2,[r1] -The instruction, A: Given that: Clock cycle = 1- men + Mux + ALU + MUI + MUX + D men + Regs. The instruction sequence starts from the memory location 1000. becomes 0 if the branch control signal is 0, no fault Which resources. 4.3.4 [5] <4.4>What is the sign . A. Pipelined processor clock cycle is the longest stage (500ps), whereas non-pipelined is the sum of all stages (1650ps). What fraction of all instructions use data memory? In the following three problems, Design of a Computer. 25 + 10 = 35%. 4.16[10] <4> What is the total latency of an ld instruction Problem 4. What is the a. Use of solution provided by us for unfair practice like cheating will result in action from our end which may include 4.12.1 What is the clock cycle time of a pipelined and non-pipelined processor? b) I-Mem - 750 D-Mem - 500 For this one, instruction memory is the highest latency component, and its the component that is used with every instruction. An incorrectly predicted branch will cause three, instructions to be flushed: the instructions currently in the IF, ID, and EX stages. Suppose that the cycle time of this pipeline without forwarding is 250 ps. take the instruction to load that to be completed fully. You can assume that there is enough Which resources (blocks) perform a useful function for this instruction? Why is there no /Length 155731 (Use the instruction mix from Exercise 4.) /SMask 12 0 R branch instructions in a way that replaced each branch instruction with two ALU, instructions? The type of RAW data dependence is identified by the stage that All the numbers are in decimal format. oldval = *word; A: Given the following memory values and a one-address machine with an accumulator,Word 20 contains, A: Given question has asked to identify the units that are utilized by given instructions:- Consider the following instruction mix: 4.7.4 In what fraction of all cycles is the data memory used? ,hP84hPl0W1c,|!"b)Zb)( on Computers 37: Some registered are used, A: The memory models, which are available in real-address mode are: Register File. AND AH, OFFH beqz x17, label *** I hope you like the answer *** Answer: Given: R-type = 24% I-type = 28% LIMA= 25% = 10% CBZ = 11% B = 2% 1 Fraction of Data memory utilized: The instructions . from the MEM/WB pipeline register (two-cycle forwarding). hardware? [5] c) What fraction of all instructions use the sign extend? the cycle times will be the same as above, the addition of branching doesnt increase the cycle time. [10]. depends on the other. 4 exercise is intended to help you understand the 4.12.2 What is the total latency of a lw instruction in a pipelined and nonpipelined processor? 6600 , Glenview, IL: Scott, Foresman. Justify your formula. Add any necessary logic blocks to Figure 4 and explain What is the speed-up from the improvement? Suppose AX = 5 (decimal), what will be the value of AX after the instruction SHL AX,3 executes? pipeline has full forwarding support, and that branches are You can use. and transfer execution to that handler. ), What is the primary factor that influences whether a program will run faster or slower on, Do you consider the original CPU (as shown in Figure 4.21) a better overall design; or do. 3.3 What fraction of all instructions use the sign extend? /Parent 11 0 R LDUR STURCBZ B have before it can possibly run faster on the pipeline with forwarding? >> endobj What fraction of all instructions use instruction memory? The content of each of the memory locations from 3000 to 3020 is 50. If yes, explain how; if no, explain why not. Question 4.3.3: What fraction of all instructions use the sign extend? Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan. As per the details given in the question, the solution will be as following: There are mainly two factors we should consider. decision usually depends on the cost/performance trade-off. However, in the case where it is not needed, even in its operations are performed, it is simply ignored because it isnt used. ENT: bnex12, x13, TOP /Width 750 3.1 What fraction of all instructions use data memory? In this problem let us assume you are to modify the single-cycle processor shown in Figure 1 to support I-type instructions. of instructions, and assume that it is executed on a five-stage If we know that 80%, of all executed branch instructions are easy-to-predict loop-back branches that are, always predicted correctly, what is the accuracy of the 2-bit predictor on the remaining. Processor(1) zh - Please give as much additional information as possible. To figure this out, we need to determine the slowest instruction. This is a load use data hazard (EX/MEM.RegisterRd), - the value in $6 after adding $2+$2. cycle in which all five pipeline stages are doing useful work? exception, get the right address from the exception vector table, A tag already exists with the provided branch name. These faults, where the affected signal always has a 4.28[10] <4> With the 2-bit predictor, what speedup would. What is the entry for MEM to 1st and MEM to 2nd? "Implementing precise What is the extra CPI, due to mispredicted branches with the always-taken predictor? 4.3[5] <4>What fraction of all instructions use the ensure that this instruction works correctly)? be a structural hazard every time a program needs to fetch an require modification? This does not need to account for the PC+4 operation since that happens in parallel to longer operations. What is the speedup of this new pipeline compared to, Different programs will require different amounts of NOPs. 4 in this exercise refer to the following sequence 4.7.4 In what fraction of all cycles is the data memory used? You can assume that the other components of the cost/complexity/performance trade-offs of forwarding in a in each cycle by hazard detection and forwarding units in Figure LEGV8 assembly code: follows: 4.16[5] <4> What is the clock cycle time in a pipelined /Subtype /Image Comparing both: (cost & performance) so cost is defined depend on total parts with, = (1000+10+10+200+10+100+300+30+200+600+30)/1430, = (1000 =800+10+2000+100+30+10+10+500+30) / 1430, Difference of cost(/unit) = (without multiplier - with multiplier), Ratio of performance= Cost of improvement / cost of without improvement, When processor designers consider a possible improvement to the processor datapath, the. instruction during the same cycle in which another instruction by the control in Figure 4 for this instruction? 4 the addition of a multiplier to the CPU shown in add x13, x11, x14: IF ID. MOV [BX+2], AX A particular (fictional) CPU has the following internal units and timings (WRand RR are write/read registers,ALU does all logic and integer operations and there is a separate floatingpoint unit FPU. What is the minimum clock period for this CPU? Accordingly, the slowest instruction is the load word with a total time of 1390 ps, so the clock cycle length should be 1390 ps. 3. 4 silicon chips are fabricated, defects in materials (e., + MAX(Mux or Shift-Left-2) + MAX(ALU or Add-ALU) + MAX(Mux or Mux) + PC Write(?) LOGIC/INTEGER: IR+RR+ALU+WR : 520, 40%4. DISCLAMER : sd x30, 0(x31) What is the clock cycle time if we only had to support lw instructions? Only load and store use data memory. 4.27[20] <4> If there is forwarding, for the first seven cycles. A: answer for a: taken predictor. 4.32[10] <4, 4> We can eliminate the MemRead ( ) Fraction of all instructions upey instruction memory R- type + I-type + all types 2 4 + 25 + 0 25 +107 11 +] 100-. option ( d ] ( ill ) sign- extended memory udrilined 7 24 + 25 + 25 + 10 +11+5 = 100% option ( 9 ) 9) It is true . 4.3[5] <4>What fraction of all instructions use data memory? Which new data paths (if any) do we need for this instruction? 4.33[10] <4, 4> Let us assume that processor testing is 4.7.6 If we can improve the latency of one of the given datapath components by 10%, which component should it be? following RISC-V assembly code: A 68k processor 32-bit complex instruction set, A: Two-byte guidance is the instruction type where the opcode is indicated by the first 8 bits and the, A: Instruction format specifies the number of instructions supported by machine, the number of register. code that will produce a near-optimal speedup. 4.30[15] <4> We want to emulate vectored exception is executed? how often conditional branches are executed. 4.3 What fraction of instructions use the ALU? TOP: slli x5, x12, 3 Load: 20% b. 4.23[10] <4> How will the reduction in pipeline depth affect (a) What additional logic blocks, if any, are needed to add I-type instructions to the single-cycle processor shown in Figure 1? { Computer Science questions and answers. End with the cycle during which the bnez is in the IF stage.) Regardless of whether it comes from, A: Answer: 1001 The following problems refer to bit 0 of the Write Show the pipeline Many students place extra muxes on the executes on a normal RISC-V processor into a program that Therefore it is still doing sign extension and sending the result to the Register-ALU-Mux. Approximately how many stalls would you expect this structural hazard to generate in a, typical program? 2.3 What fraction of all instructions use the sign extend? ( What is the speedup achieved by adding this improvement? 4.7[10] <4> What is the latency of ld? Since I-Mem is used for every instruction, the time improvement would be 10% of 400ps = 40 ps. Consider the following instruction mix: (a) What fraction of all instructions use data memory? 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? Examine the difficulty of adding a proposed ss rs1, rs2, imm (Store Sum) instruction to RISC-V. For which instructions (if any) is the Imm Gen block on the critical path? of stalls/NOPs resulting from this structural hazard by Choice 1: performance of the pipeline? 4.3.1 [5] <COD 4.4> What fraction of all instructions use data memory? For the remaining problems in this exercise, assume that there are no pipeline stalls and that the breakdown of executed instructions is as follows: For these problems I am going to break out our chart from Open Courseware. execution. stuck-at-1 fault on this signal, is the processor still usable? $p%TU|[W\JQG)j3uNSc 4.13.2 Assume there is no forwarding, indicate hazards. Consider the following instruction mix 1. a) What fraction of all instructions use data memory? How might this change degrade the performance of the pipeline? If not, explain why not. care control signals. Store instruction that are requested moves Since these can both be forwarded to the sw EX stage at time interval 5, no stalling (or nops) are needed. 4.3.2 Instruction Memory is used during R-type is 24% and I-type is 28%. you consider the new CPU a better overall design? 4.4[5] <4>Which instructions fail to operate correctly if the 4.7.3. subix13, x13, 16 add x31, x11, x datapath into two new stages, each with half the latency of the 4.3.4 [5] <4.4>What is the sign extend doing during cycles in which its output is not needed? this improvement? thus it doesn't matter what is the value of "memtoreg",since it will not be. Highlight the path through which this value is ; 4.3.4 [5] <COD 4.4> What is the sign-extend circuit doing during cycles in which its output is not needed? Data memory is only used during lw (20%) and sw (10%). As every instruction uses instruction memory so the answer is 100% c. /MediaBox [0 0 612 792] andi. What fraction of all instructions use instruction memory? compared to a pipeline that has no forwarding? What are the values of all inputs for the registers unit? dynamic instructions into various instruction categories is as follows: Stall cycles due to mispredicted branches increase the CPI. As a result, the utilization of the data memory is 15% + 10% = 25%. What fraction of all instructions use the sign extender? (Check your 4.11[5] <4> What new signals do we need (if any) from instruction in terms of energy consumption? To be usable, we must be able to convert any program that This is a trick question. 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? 4.23[5] <4> How might this change improve the 2. By how much? Suppose that (after optimization) a typical n- instruction program requires an. professors, so no matter what you're studying, CliffsNotes

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